1. Field of the Invention
The present invention relates to an interface circuit which transmits a digital signal at a high speed.
2. Description of the Related Art
Recently, it is increasingly demanded that interface circuits, employed in I/O sections of semiconductor integrated circuits, be operated at a high speed with less noise. Examples of high-speed interface circuits are a small-amplitude differential output circuit, typically known as an LVDS (Low Voltage Differential Signalling), and a small-amplitude output circuit, typically known as a GTL (Gunning Transceiver Logic) or an HSTL (High Speed Transceiver Logic).
FIG. 1 is a circuitry diagram showing the structure of an example of an LVDS type interface circuit. The first example of the interface circuit comprises: a drive circuit 7 which differentially outputs an output signal in accordance with an input signal VIN to a terminating resistor RL connected between two output terminals DO and XDO; and a bias circuit 6 which controls an output current I of the drive circuit 7.
The drive circuit 7 comprises: a buffer 71 which performs non-inverting output of an input signal VIN; an inverter 72 which performs inverting output of an input signal VIN; a P-channel MOSFET (hereinafter referred to as an P-MOSFET) P11 and an N-channel MOSFET (hereinafter referred to as an N-MOSFET) N11 which are driven by the buffer, a P-MOSFET P12 and an N-MOSFET N12 which are driven by the inverter, and a P-MOSFET PC11 which serves as a constant current source for making a predetermined output current flow to the terminating resistor RL connected between the two output terminals DO and XDO.
The bias circuit 6 comprises: a fixed resistor RP11; and a P-MOSFET PX11 which constantly controls a current IRP to flow to the fixed resistor RP11.
In such a structure, when the input signal VIN is at a low level, the P-MOSFET P11 is ON, and the N-MOSFET N11 is OFF, the P-MOSFET P12 is OFF, and the N-MOSFET N12 is ON. Thus, as described iwth arrow D in FIG. greater than  1, the output current I flows through a path along the P-MOSFET PC11, the P-MOSFET P11 and the N-MOSFET N12. At his time, a low level voltage (VCL) is out put to the output terminal DO, whereas a high level voltage (VOH) is out put to the output terminal XDO.
In the first example of the interface circuit, the P-MOSFET PX11 and the P-MOSFET PC11 operate in their saturation range, and the dimensions of the respective transistors are designed such that constants of the transistors are set at a predetermined ratio. In this structure, the P-MOSFET PX11 and the P-MOSFET PC11 operate under the Miller effect, thus a current IRP flowing through the P-MOSFET PX11 and a current I flowing through the P-MOSFET PC11 are in proportion to each other
Accordingly, when having the structure of the bias circuit 6 as shown in FIG. 1, any variation in the current IRP which may occur as a result of a variation in the source voltage VDD or any difference (deviation) occurring in transistors in the manufacturing processes can be reduced. In addition, a variation in the output current I of the drive circuit 7 which is in proportion to the current IRP of the bias circuit 6 can be reduced.
FIG. 2 is a circuitry diagram showing the structure of the second example of an interface circuit which is disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H3-283713. The second example of the interface circuit shown in FIG. 2 comprises: a drive circuit 9 comprising a P-MOSFET P15 and an N-MOSFET N13 which are connected in series between a power source VDD and a ground potential; an NAND circuit 83 which supplies the P-MOSFET P13 in the drive circuit 9 with a gate voltage VPO; a NOR circuit 84 which supplies the N-MOSFET N13 with a gate voltage VNG; and a sense amplifier 81 and a sense amplifier 82 which control a voltage of an output terminal DO in the drive circuit 9 to be in a predetermined value. The output terminal DO is connected to a reference voltage VTT along a transmission path via a terminating resistor RL.
In such a structure, a control voltage VOH for controlling a voltage of the output terminal DO in the drive circuit 9 into a high level is input to a non-inverting input terminal of the sense amplifier 81 serving as a differential amplifier. A control voltage VOL for controlling a voltage of the output terminal DO in the drive circuit 9 into a low level is input to a non-inverting input terminal of the sense amplifier 82 serving as a differential amplifier.
The voltage of the output terminal DO is fed back to inverting input terminals of the respective sense amplifiers 81 and 82. Thus, the sense amplifier 81 controls the voltage of the output terminal DO to a voltage level of VOH, whereas the sense amplifier 82 controls the voltage of the output terminal DO to a voltage level of VOL.
Either one of the NAND circuit 83 and the NOR circuit 84 supplies the MOSFET included in the drive circuit 9 with a gate voltage, in accordance with the conditions of the input signal VIN. The output voltages of the respective NAND circuit 83 and NOR circuit 84 are so controlled that their voltage values are in proportion to the value of the output voltages of the respective sense amps 81 and 82.
Therefore, when the input signal VIN is at a high level, the voltage of the output terminal DO is controlled to be at a voltage level of VOH by the sense amp 81, resulting in making the current IH flow to the terminating resistor RL. On the contrary, when the input signal VIN is at a low level, the voltage of the output terminal DO is controlled at a voltage level of VOL, resulting in making the current IL flow to the terminating resistor RL.
Accordingly, having controlled the output current IL or IH to flow to the terminating resistor RL in accordance with the conditions of the input signal VIN, the voltage of the output terminal DO varies.
In the first example of an interface circuit shown in FIG. 1, a variation of the current IRP, resulting from a source voltage variation or any difference occurring in transistors in the manufacturing processes, can not sufficiently be reduced. This entails problems that a current variation is large in the output current I and an amplification variations is also large in the output voltage.
Variations in the current IRP, which variations occur in the bias circuit as a result of a variation in a source voltage or any difference occurring in transistors in the manufacturing processes, will now be explained with reference to FIGS. 3 and 4.
FIG. 3 is a circuitry diagram showing the structural example of a bias circuit employed in an interface circuit. FIG. 4 is a graph showing characteristics of output currents and output voltages with reference voltage of a gate voltage to be applied to the bias circuit illustrated in FIG. 3.
In the bias circuit shown in FIG. 3, a P-MOSFET PX12 and a fixed resistor RP12 are connected in series between a power source VDD and a ground potential. In such a structure, when the power source VDD is set at 3.6 V or 2.7 V, the relationship between the current IRP and the output voltage VRP with reference to the gate voltage VO is as shown in FIG. 4.
In the first example, as shown in FIG. 1, of the bias circuit, the gate voltage and the drain voltage of the P-MOSFET PX11 are the same (VGP). Accordingly, based on the characteristics shown in FIG. 4, the current IRP is xe2x88x921.9 mA when the source voltage VDD is 2.7 V, whereas the current IRP is xe2x88x923.3 mA when the source voltage VDD is 3.6 V.
Accordingly, in the bias circuit having the structure shown in FIG. 1, when the source voltage VDD varies from 2.7 V to 3.6 V, the output current I of the interface circuit which is in proportion to the current IRP varies as well.
In the second example of the interface circuit shown in FIG. 2, when the input signal VIN to be output, there is a delay before the voltage of the output terminal DO varies in response to the variation in the output voltage of the NAND circuit 83 or NOR circuit 84. Further, there is a delay before an output voltage of the NAND circuit or NOR circuit varies when the sense amp 81 or 82 responses to the variation in the voltage of the output terminal DO. Accordingly, when the voltage of the output terminal DO is switched from VOH to VOL or from VOL to VOH, a drawback is that a noise occurs.
FIG. 5 is a waveform diagram showing operations of the interface circuit shown in FIG. 2. Illustrated in FIG. 5 are the gate voltage of the output terminal DO and the gate voltage of the P-MOSFET, when the voltage of the output terminal DO switches from VOL to VOH. As shown in FIG. 5, in response to switching of the voltage of the output terminal DO from VOL to VOH, the sense amp 81 makes the output voltage VPG of the NAND circuit 83 vary with a delay of a delay period T1, along with an increase in the voltage of the output terminal DO. Hence, the voltage of the output terminal DO continuously increases during the period of T1+T2, even if it exceeds the control voltage VOH, resulting in generating a spike noise. Similarly, when the voltage of the output terminal DO switches from VOH to VO, a noise is generated.
In the second example of the interface circuit, two sense amps are necessary, causing a large size of the circuit to be manufactured.
As a technique having relevance to the present invention, for example, Unexamined Japanese Patent Application KOKAI Publication No. S61-244120 discloses a logical signal detecting output circuit which converts an output signal of a differential amplifier into an ECL level signal. Unexamined Japanese Patent Application KOKAI Publication No. H2-27807 discloses a technique for a differential amplifier, wherein the Miller capacitance is set small and the frequency characteristic of the amplifier is set at a broad band. Further, Unexamined Japanese Patent Application KOKAI Publication No. H5-327472 discloses an output circuit for obtaining a large driving current and voltage amplification. Unexamined Japanese Patent Application KOKAI Publication No. H6-326591 discloses an output circuit which can perform small-amplification operations to operate at a high speed. Furthermore, Unexamined Japanese Patent Application KOKAI Publication No. H9-8637 discloses an output circuit for outputting an accurate output signal without any high accuracy resistance. However, the techniques discloses in these publications do not solve the above mentioned problems of the first and second examples of the interface circuits.
The first object of the present invention is to provide an interface circuit, wherein a variation in an output current which variation occurs as a result of a variation in a source voltage or any difference occurring in transistors in the manufacturing processes, is controlled.
The second object of the present invention is to provide an interface circuit, wherein a variation in amplification of an output current, which variation occurs as a result of a variation in a source voltage or any difference occurring in transistors in the manufacturing processes, is controlled.
The third object of the present invention is to provide an interface circuit having a simple structure and being operable at speed.
The fourth object of the present invention is to provide an interface circuit wherein any noise is prevented from occurring and which is operable at speed.
In order to achieve the above-described objects, according to the first aspect of the present invention, there is provided an interface circuit which outputs an output signal in accordance with an input signal to at least one end of a load, the interface circuit comprising:
a load;
a driving circuit having a first resistor which supplies a first constant current to the load and a switching circuit which supplies the first constant current to the load; and
a bias circuit having a fixed resistor, a second transistor which is connected with the fixed resistor and which is operable with the first transistor under a Miller effect, and a control circuit which controls a voltage applied to control terminals of the first and second transistor and an output voltage of the second transistor to be at predetermined voltage ratio.
In the interface circuit.
each of the first and second transistor may include a current path and a control terminal;
the current path of the first transistor may be connected to the switching circuit;
the current path of the second transistor may be connected to the fixed resistor; and
the interface circuit may comprise a differential amplifier whose non-inverting input terminal receives a predetermined voltage, and whose inverting input terminal receives a voltage of a connection node between the second transistor and the fixed resistor, and a output terminal which applies an output voltage at the control terminals of the first and second transistor.
In the interface circuit,
the switching circuit may switch a flow direction of a current flowing through the load from one end to the other end and from the other end to the one end.
The interface circuit may further comprise:
a second driving circuit having a third transistor which supplies a second constant current to the load and a second switching circuit which supplies the second constant current to the load;
a second bias circuit having a second fixed resistor, a fourth transistor which is connected with the second fixed resistor and which is operable when the third transistor under a Miller effect; and a second control circuit which controls a voltage applied to the control terminals of the third and fourth transistors and an output voltage of the fourth transistor to be at a predetermined voltage ratio.
In the interface circuit:
each of the third and fourth transistors may include a current path and a control terminal;
the current path of the third transistor may be connected to the second switching circuit;
the current path of the fourth transistor may be connected to the second fixed resistor;
the interface circuit further may comprise a second differential amplifier whose non-inverting input terminal receives a second predetermined voltage, and whose inverting input terminal receives a voltage of a connection node between the fourth transistor and the second fixed resistor, and an output terminal which applies an output voltage at the control terminals of the third and fourth transistors.
In the interface circuit,
the first and second transistors may respectively comprise P-channel MOS FETs or N-channel MOS FETS.
In the interface circuit:
each of the first and second transistors may respectively comprise P-channel MOS FETs or N-channel MOS FETS: and
the third and fourth transistors may respectively comprise N-channel MOS FETs or P-channel MOS FETs.
According to the second aspect of the present invention, there is provided an operating method of an interface circuit which outputs an output signal in accordance with an input signal to at least one end of a load, the operating method comprising:
controlling and applying a common voltage to gates of a first transistor and a second transistor whose current path is connected to a resistor so that a voltage at a connection point of the resistor and the second transistor is a predetermined value, thereby to make the first and second transistors operate under a Miller effect; and
supplying, in response to an input signal, a current which flows through the first transistor to a load, thereby outputting an output signal between both ends of the load or at one end of the load.
The operating method of an interface circuit may further comprise:
controlling and applying a second common voltage to gates of a third transistor and a fourth transistor whose current path is connected to a second resistor so that a voltage at an connection point of the second resistor and the fourth transistor is second predetermined value, thereby to make the third and fourth transistor operate under a Miller effect; and
supplying, in response to an input signal, a current which switchingly flows through the first transistor and the third transistor to the load.